| Autor: |
R. Sarma, C. Bhargava, S. Jain |
| Jazyk: |
angličtina |
| Rok vydání: |
2020 |
| Předmět: |
|
| Zdroj: |
Bulletin of the Polish Academy of Sciences: Technical Sciences, Vol 68, Iss No. 4 (i.a. Special Section on Advances in Electrical Power Engineering), Pp 835-844 (2020) |
| Druh dokumentu: |
article |
| ISSN: |
2300-1917 |
| DOI: |
10.24425/bpasts.2020.134182 |
| Popis: |
Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of –(7.96875)10 to +(7.96875)10. The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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