| Autor: |
Wu Jianxiao, Wang Peng, Wu Tao, Gao Peng, Chen Wentao |
| Jazyk: |
čínština |
| Rok vydání: |
2019 |
| Předmět: |
|
| Zdroj: |
Dianzi Jishu Yingyong, Vol 45, Iss 9, Pp 65-70 (2019) |
| Druh dokumentu: |
article |
| ISSN: |
0258-7998 |
| DOI: |
10.16157/j.issn.0258-7998.190593 |
| Popis: |
SERDES(serial de-serialization) technology has become the mainstream physical layer specification of high-speed interface due to its high transmission rate and strong capacity of resisting disturbance. However, the upper PCS(physical coding sublayer) needs to set elastic buffering, code, encode and do other functions, so the system transmission delay is high. SERDES cannot be directly applied to delay sensitive applications such as processor direct connection. This paper introduces a design of PCS architecture based on synchronous phase compensation buffer(SPCB), which can be applied to delay sensitive SERDES transmission system. This architecture features high throughput and ultra-low latency. With a custom SPCB, the transmission reception path delay is about 10 ns at 32 Gb/s per lane, which is about half of the typical PCS delay in the industry, reaching the level of Intel(QPI) and AMD(HT) interface. This PCS architecture can be realized through 28 nm/16 nm/7 nm chip manufacturing tech, and has been applied to a variety of domestic processor. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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