| Autor: |
Piyush Kumar, Da Eun Shim, Siri Narla, Azad Naeemi |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
|
| Zdroj: |
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 10, Pp 13-21 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2329-9231 |
| DOI: |
10.1109/JXCDC.2024.3357625 |
| Popis: |
While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7 nm node. Based on interconnect resistance values from technology computer-aided design (TCAD) simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin–orbit torque (SOT) MRAM and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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