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This paper presents a simulation-based environment for verification of static task scheduling methodology in a time predictable system. Different types of processed tasks are distinguished and presented a unified system design methodology consisting of the selection of real time system configuration, task mapping, scheduling, and generation of a sequence of task identifiers to control the interleaved pipeline. An original Worst Case Timing Analyzer (WCTA) has been developed to automate the design process. The methodology was introduced into the original PRET (PREcision Timed) architecture recently presented (Antolak and Pulka, 2020), (Antolak and Pulka, 2021). The PRET system was implemented on a Virtex7 FPGA (Field Programmable Gate Array) platform. A dedicated verification environment is proposed that allows on-line real time system monitoring, analysis of timing parameters, and comparing the results with initial requirements and design constraints. The practical experiments presented in the paper proved the correct operation of the author’s hardware architecture. The obtained results confirmed the validity of the proposed scheduling method and the concept of calculating the execution times of tasks before they are started, which allows for optimal hardware matching to the tasks to be performed. |
