| Autor: |
Cai Hongyan, Du Tao, Meng Xianggang, Li Guofeng, Liang Ke, Chen Xinwei |
| Jazyk: |
čínština |
| Rok vydání: |
2018 |
| Předmět: |
|
| Zdroj: |
Dianzi Jishu Yingyong, Vol 44, Iss 8, Pp 27-30 (2018) |
| Druh dokumentu: |
article |
| ISSN: |
0258-7998 |
| DOI: |
10.16157/j.issn.0258-7998.174735 |
| Popis: |
MBIST(Memory Built-In Self-Test) technology has extensive application in the memory test. In view of the traditional BIST controller register transfer level description language design process is relatively complicated, special flexibility EDA tools to define algorithm flexibility is poor, and the circuit structure is fixed, this paper proposes the use of high-level synthesis tools BIST controller design method. This paper takes SRAM as the object, describes the MARCH algorithm in C language, and uses port allocation, pipeline optimization and array segmentation to optimize the design. Finally, with the tools of the FPGA platform it verifies and evaluates the function reliability and scle controllability of the high-level synthesis synthesized RTL code level circuit. Compared with the two traditional methods, the limitation of algorithm implementation and circuit structure is eliminated, and the implementation period of the algorithm is reduced. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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