| Autor: |
Yusaku Shiotsu, Satoshi Sugahara |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
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| Zdroj: |
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 8, Iss 2, Pp 134-144 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2329-9231 |
| DOI: |
10.1109/JXCDC.2022.3225744 |
| Popis: |
A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating (PG) using ULVR at an ultralow voltage (< EMP), which can be applied to fully connected layers (FCLs) with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply–accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA macro can show a high energy efficiency of 65 TOPS/W for FCLs. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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