| Autor: |
Zhao, Jerry, Grubb, Daniel, Rusch, Miles, Wei, Tianrui, Anderson, Kevin, Nikolic, Borivoje, Asanovic, Krste |
| Rok vydání: |
2024 |
| Předmět: |
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| Druh dokumentu: |
Working Paper |
| Popis: |
While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations. |
| Databáze: |
arXiv |
| Externí odkaz: |
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