MARTE based design flow for Partially Reconfigurable Systems-on-Chips

Autor: Quadri, Imran Rafiq, Muller, Alexis, Meftali, Samy, Dekeyser, Jean-Luc
Přispěvatelé: Contributions of the Data parallelism to real time (DART), Laboratoire d'Informatique Fondamentale de Lille (LIFL), Université de Lille, Sciences et Technologies-Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lille, Sciences Humaines et Sociales-Centre National de la Recherche Scientifique (CNRS)-Université de Lille, Sciences et Technologies-Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lille, Sciences Humaines et Sociales-Centre National de la Recherche Scientifique (CNRS)-Inria Lille - Nord Europe, Institut National de Recherche en Informatique et en Automatique (Inria), Université de Lille, Sciences et Technologies-Institut National de Recherche en Informatique et en Automatique (Inria)-Université de Lille, Sciences Humaines et Sociales-Centre National de la Recherche Scientifique (CNRS)
Jazyk: angličtina
Rok vydání: 2009
Předmět:
Zdroj: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09)
17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Oct 2009, Florianapolis, Brazil
Popis: International audience; Systems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements.
Databáze: OpenAIRE