Impact of Line-Edge Roughness on FinFET Matching Performance
| Autor: | Nicolo'Attilio Speciale, K. De Meyer, Malgorzata Jurczak, Rita Rooyackers, Emanuele Baravelli, Abhisek Dixit |
|---|---|
| Přispěvatelé: | E. Baravelli, A. Dixit, R. Rooyacker, M. Jurczak, N. Speciale, K. De Meyer |
| Rok vydání: | 2007 |
| Předmět: |
Engineering
business.industry Transistor Hardware_PERFORMANCEANDRELIABILITY Integrated circuit Electronic Optical and Magnetic Materials law.invention CMOS law Logic gate MOSFET Hardware_INTEGRATEDCIRCUITS Electronic engineering Node (circuits) Static random-access memory Electrical and Electronic Engineering business Critical dimension |
| Zdroj: | IEEE Transactions on Electron Devices. 54:2466-2474 |
| ISSN: | 0018-9383 |
| Popis: | As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|