Joint symbol and chip synchronization for a burst-mode-communication superregenerative MSK receiver
| Autor: | P. Pala-Schonwalder, Alexis Lopez-Riera, F. Xavier Moncunill-Geniz, Jordi Bonet-Dalmau, R. Giralt-Mas, Francisco del Aguila-Lopez |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Enginyeria Minera, Industrial i TIC, Universitat Politècnica de Catalunya. CIRCUIT - Grup de Recerca en Circuits i Sistemes de Comunicació |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Computer science
Modulació digital 02 engineering and technology Synchronization Superregenerative receiver Instantaneous phase Senyal Teoria del (Telecomunicació) VHDL Demodulation (Electronics) Digital modulation 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Field-programmable gate array Burst mode (computing) computer.programming_language RF receivers Frequency-shift keying Network packet 020208 electrical & electronic engineering Physical layer 020206 networking & telecommunications Signal theory (Telecommunication) MSK demodulation Chip Enginyeria de la telecomunicació::Processament del senyal [Àrees temàtiques de la UPC] Low-power communication receivers computer |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) Recercat. Dipósit de la Recerca de Catalunya instname |
| DOI: | 10.1109/TCSI.2016.2636022 |
| Popis: | In this paper we describe a superregenerative (SR) MSK receiver able to operate in a burst-mode framework where synchronization is required for each packet. The receiver is based on an SR oscillator which provides samples of the incoming instantaneous phase trajectories. We develop a simple yet effective technique to achieve joint chip and symbol synchronization within the time limits of a suitable preamble. We develop some general results and focus on the case of the IEEE 802.15.4 MSK physical layer. We provide details on a VHDL implementation on an FPGA where the most complex digital processing block is an accumulator. Simulation and experimental results are provided to validate the described technique. |
| Databáze: | OpenAIRE |
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