Design of a 12-bit SAR ADC with digital self-calibration for radiation detectors front-ends
| Autor: | Andrea Di Salvo |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
capacitor mismatch
digital background calibration low power SAR ADC Signal processing Spurious-free dynamic range Computer science 12-bit 020208 electrical & electronic engineering Successive approximation ADC 02 engineering and technology Chip law.invention Capacitor Effective number of bits CMOS law 0202 electrical engineering electronic engineering information engineering Electronic engineering |
| Zdroj: | PRIME |
| DOI: | 10.1109/prime.2019.8787843 |
| Popis: | The paper describes the design of a 12-bit SAR ADC with digital self-calibration to be used in multi-channel ASICs for radiation detectors employed in nuclear and particle physics. In these systems, a highly segmented sensor is coupled to a front-end chip with many channels operating in parallel. The details of the signal processing to be performed depend on the particular applications, but in several cases it is necessary to embed on the front-end chip a large number of analog-to-digital converters (32 or more) that have to operate simultaneously. Typical requirements for the converter are a resolution in the 10–12 bits range, a sampling frequency above 20 Msamples/sec, very low power consumption and good radiation hardness. The ADC discussed in this paper is based on a fully differential SAR architecture assisted by a digital background calibration that relies on the Offset Double Conversion (ODC) method. The algorithm uses an analog offset injection to compute the intrinsic error of the ADC conversion due to mismatch among the DAC capacitors. The approach allows to find a set of weights, which are then applied at each conversion to achieve a real-time correction. The ADC was preliminary modelled with a high level C++ code. Physical implemented in both in 110 nm and 65 nm CMOS technologies is underway. The paper focuses on the design and hardware implementation of the calibration algorithm. The average ENOB after correction is incremented by 4 bits by using a 15% random capacitor mismatch. The SFDR is hold below −90 dB. The power consumption of the calibration circuit is 5.6 mW and 3 mW respectevely for 110 nm and 65 nm node. A further study investigated how many bit have to be calibrated to hold a reasonable ENOB. |
| Databáze: | OpenAIRE |
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