NISC-based MIMO MMSE Detector
| Autor: | Youssef Atat, Amer Baghdadi, Yasser Mohanna, Mostafa Rizk, Michel Jezequel |
|---|---|
| Přispěvatelé: | School of Engineering [Lebanese International University] (SOE/LIU), Lebanese International University (LIU), Lab-STICC_IMTA_CACS_IAS, Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT), Département Electronique (IMT Atlantique - ELEC), IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Faculty of Sciences [Lebanese University], Lebanese University [Beirut] (LU) |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Computer science
MMSE-IC MIMO 02 engineering and technology [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI] [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Field-programmable gate array FPGA Flexibility (engineering) turbo-detection NISC business.industry Processor design [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic 020208 electrical & electronic engineering Detector iterative processing 020206 networking & telecommunications General Medicine [SPI.TRON]Engineering Sciences [physics]/Electronics Hardware and Architecture [INFO.INFO-IT]Computer Science [cs]/Information Theory [cs.IT] [INFO.INFO-ES]Computer Science [cs]/Embedded Systems hardware implementation [INFO.INFO-DC]Computer Science [cs]/Distributed Parallel and Cluster Computing [cs.DC] business Computer hardware |
| Zdroj: | Journal of Circuits, Systems, and Computers Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2020, pp.2150069. ⟨10.1142/S0218126621500699⟩ |
| ISSN: | 0218-1266 |
| DOI: | 10.1142/S0218126621500699⟩ |
| Popis: | Several application-specific processor design approaches have been proposed and investigated to cope with the emerging flexibility requirements jointly associated with the maximum performance efficiency and minimum implementation area and power consumption. Dynamic scheduling of a set of instructions generally leads to an overhead related to instruction decoding. To mitigate this overhead, other approaches have been proposed using static scheduling of datapath control signals. In this context, No-Instruction-Set-Computer (NISC) concept have been introduced considering that a dedicated processor to a specific application does not need an instruction set especially when it is programmed by its designers and not by its users. In this paper, the hardware architecture design of flexible NISC-based architecture design dedicated for minimum mean-squared error (MMSE) linear detection is presented. The devised design, which is used in iterative turbo-receiver, fulfills the performance requirements of emergent wireless communication standards with throughput reaching that of LTE-Advanced. FPGA hardware implementation of the detector architecture achieves a maximum throughput of 115.8 Mega symbols per second for [Formula: see text] and 6.4 Mega symbols per second for [Formula: see text] MIMO systems for an operating clock frequency of 202.67[Formula: see text]MHz. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|