A Review on Reduced Switch Count Multilevel Inverter Topologies
| Autor: | Balwinder Singh Surjan, Prabhu Omer, Jagdish Kumar |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Voltage rating
General Computer Science Computer science 020209 energy H-bridge 02 engineering and technology Network topology even power distribution reduced switch count Multilevel inverter Component (UML) 0202 electrical engineering electronic engineering information engineering General Materials Science Power semiconductor device symmetric source business.industry 020208 electrical & electronic engineering General Engineering Electrical engineering H bridge Power (physics) Semiconductor Key (cryptography) fundamental switching Multilevel inverters lcsh:Electrical engineering. Electronics. Nuclear engineering business lcsh:TK1-9971 Voltage |
| Zdroj: | IEEE Access, Vol 8, Pp 22281-22302 (2020) |
| ISSN: | 2169-3536 |
| Popis: | Multilevel Inverters (MLIs) are becoming more and more popular in medium and high power applications. This is due to several inherent advantages of MLI over two-level inverters such as high-quality output, lower device ratings, and several others. While the classical topologies are still having applications in most of the key areas, there is a growing interest in newer multilevel topologies with an objective of reducing power semiconductor device count, gate drivers and/or isolated DC sources. In this paper, a comprehensive review of some of the recently proposed newer multilevel inverter topologies with the abovementioned objectives is presented. In this article, a detailed investigation in terms of total power semiconductor switch count, number of DC sources, passive component requirement, highest switch voltage rating, total standing voltage etc. has been presented. |
| Databáze: | OpenAIRE |
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