On-chip decoupling capacitor optimization using architectural level prediction

Autor:	D.S. Wills, P. Pant, M.D. Pant
Rok vydání:	2002
Předmět:	Very-large-scale integration Engineering business.industry Pentium Integrated circuit Decoupling capacitor law.invention Microarchitecture Capacitor Microprocessor Hardware and Architecture law Electronic engineering Electrical and Electronic Engineering business Software Decoupling (electronics)
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:319-326
ISSN:	1557-9999 1063-8210
DOI:	10.1109/tvlsi.2002.1043335
Popis:	Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9767400c5f5c2dbadfc558fa354de2dd https://doi.org/10.1109/tvlsi.2002.1043335 Zobrazit plný text záznamu