Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)
| Autor: | C. T. Wang, C.H. Tsai, M. F. Chen, Douglas Yu, Terry Ku, W. C. Chiou |
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| Rok vydání: | 2020 |
| Předmět: |
Materials science
Stacking 02 engineering and technology High Bandwidth Memory 01 natural sciences law.invention Stack (abstract data type) law 0103 physical sciences Thermal 0202 electrical engineering electronic engineering information engineering Static random-access memory Electrical and Electronic Engineering 010302 applied physics Very-large-scale integration Dynamic random-access memory business.industry 020208 electrical & electronic engineering Bandwidth (signal processing) Small Outline Integrated Circuit 020206 networking & telecommunications Electronic Optical and Magnetic Materials Optoelectronics business Electrical efficiency Dram |
| Zdroj: | 2020 IEEE Symposium on VLSI Technology. |
| Popis: | A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is proposed and implemented for 3-D memory integration, such as 3-D static random access memory (SRAM) or dynamic random access memory (DRAM) cube. It extends not only 2-D pin count to 12000/mm2 but also overcomes the obstacle of the stacking height. 4-Hi, 8-Hi, and 12-Hi stacks, each with 1 base die and 4, 8, and 12 dies, respectively, are realized and demonstrated in this article. The daisy chains in the 4-Hi/8-Hi/12-Hi structures incorporating over 10 000 through silicon vias (TSVs) and bonds are tested with liner ${I}-{V}$ curves, which indicates the good bonding and stacking quality. The electrical link from base controller to top DRAM for 12-Hi and 16-Hi high bandwidth memory (HBM) structure is built up to study the bandwidth (BW) and power efficiency. Compared to $\mu $ bump technology, the BW for the 12-Hi and 16-Hi structures using SoIC bonding shows the improvement of 18% and 20%, respectively, under same pin pitch and the power efficiency has the improvement of 8% and 15%. For thermal performance, the 12-Hi and 16-Hi SoIC-bond structure is 7% and 8% better than those using $\mu $ bump technology, respectively. With this innovative SoIC bonding and stacking technology, the bond pitch is scalable to sub-micrometer and the die thickness is manageable to be thinner, which are prospected for the application of higher BW 3-D memory with tera byte (TB)/s per stack. |
| Databáze: | OpenAIRE |
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