Challenges for silicon technology scaling in the Nanoscale Era
| Autor: | Tze-chiang Chen |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Moore's law
Silicon business.industry Circuit design media_common.quotation_subject Transistor Electrical engineering chemistry.chemical_element Hardware_PERFORMANCEANDRELIABILITY Dissipation law.invention chemistry CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Systems architecture business media_common |
| Zdroj: | ESSCIRC |
| DOI: | 10.1109/esscirc.2009.5325955 |
| Popis: | The continuous and systematic increase in transistor density and performance, as described in “Moore's Law” [1] and guided by CMOS scaling theory [2], has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variability will be imposed by the approach toward atomistic and quantum-mechanical physics boundaries. These issues are frequently cited as the reason Moore's Law is “broken”, or why CMOS scaling is coming to an end. However, the infusion of new materials, device structures, and the exploitation of 3D-silicon integration, coupled with innovations in circuit design and system architecture, will ensure several more generations of continued CMOS development. |
| Databáze: | OpenAIRE |
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