Improved electrical performance of a sol–gel IGZO transistor with high-k Al2O3 gate dielectric achieved by post annealing
Autor: | Ji-Hoon Ahn, Esther Lee, Jee Hoon Kim, Jaeun Kim, Seung Won Lee, Tae Gun Jeong, Tae Hyeon Kim, Byung Jin Cho |
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Jazyk: | angličtina |
Rok vydání: | 2019 |
Předmět: |
Materials science
Annealing (metallurgy) lcsh:Biotechnology Gate dielectric X-ray photoelectron spectroscopy depth profiling Dielectric lcsh:Chemical technology Capacitance lcsh:Technology law.invention Indium gallium zinc oxide IGZO Post annealing law lcsh:TP248.13-248.65 General Materials Science lcsh:TP1-1185 lcsh:Science High-κ dielectric Indium gallium zinc oxide business.industry lcsh:T Research Transistor General Engineering Biasing lcsh:QC1-999 Capacitance–voltage measurement Optoelectronics Electrical bias stress stability lcsh:Q business lcsh:Physics |
Zdroj: | Nano Convergence, Vol 6, Iss 1, Pp 1-8 (2019) Nano Convergence |
ISSN: | 2196-5404 |
Popis: | We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor. Electronic supplementary material The online version of this article (10.1186/s40580-019-0194-1) contains supplementary material, which is available to authorized users. |
Databáze: | OpenAIRE |
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