Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures
| Autor: | Jean-Marc Delosme, Alix Munier-Kordon, Youen Lesparre |
|---|---|
| Přispěvatelé: | Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Informatique, Biologie Intégrative et Systèmes Complexes (IBISC), Université d'Évry-Val-d'Essonne (UEVE) |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
0209 industrial biotechnology
Theoretical computer science Dataflow Computer science Liveness 02 engineering and technology Parallel computing Synchronous Data Flow 020901 industrial engineering & automation Network on a chip Scalability 0202 electrical engineering electronic engineering information engineering Graph (abstract data type) 020201 artificial intelligence & image processing Distributed memory [INFO]Computer Science [cs] Time complexity ComputingMilieux_MISCELLANEOUS |
| Zdroj: | 2016 Euromicro Conference on Digital System Design, DSD 2016 2016 Euromicro Conference on Digital System Design, DSD 2016, Aug 2016, Limassol, Cyprus. pp.146-153, ⟨10.1109/DSD.2016.52⟩ DSD |
| DOI: | 10.1109/DSD.2016.52⟩ |
| Popis: | The search of a mapping of a Synchronous Data Flow Graph (SDFG) on a distributed architecture that achieves a given throughput while satisfying memory constraints is a difficult challenge. Solving this problem calls for evaluating throughput and buffer capacities associated to a mapping. Since the available mapping evaluation methods are not polynomial with respect to the SDFG description, mapping techniques using them are not scalable. This paper develops a polynomial method for the evaluation of any given SDFG mapping on a distributed architecture. The method is based on a simple transformation of the SDFG to model communications through a Network on Chip. The key result is that the size of the memory required in order to guarantee the liveness or a given throughput of an application may be evaluated in polynomial time. Experimentally, computing the memory size guaranteeing liveness of a mapping of a 670-node H264 graph on a 4-cluster architecture takes 70 ms on an Intel Core i5-660 processor and grows linearly with graph size. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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