High-Performance Transactions for Persistent Memories
| Autor: | Ali G. Saidi, Peter M. Chen, Steven Pelley, Thomas F. Wenisch, Aasheesh Kolli |
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| Rok vydání: | 2016 |
| Předmět: |
Speedup
Computer science 02 engineering and technology Commit Parallel computing computer.software_genre 01 natural sciences Consistency (database systems) 0103 physical sciences 0202 electrical engineering electronic engineering information engineering General Environmental Science Abstraction (linguistics) 010302 applied physics 020207 software engineering General Medicine Computer Graphics and Computer-Aided Design Durability 020202 computer hardware & architecture Non-volatile memory Operating system General Earth and Planetary Sciences Non-volatile random-access memory Persistent data structure Database transaction computer Software Dram |
| Zdroj: | ASPLOS |
| Popis: | Emerging non-volatile memory (NVRAM) technologies offer the durability of disk with the byte-addressability of DRAM. These devices will allow software to access persistent data structures directly in NVRAM using processor loads and stores, however, ensuring consistency of persistent data across power failures and crashes is difficult. Atomic, durable transactions are a widely used abstraction to enforce such consistency. Implementing transactions on NVRAM requires the ability to constrain the order of NVRAM writes, for example, to ensure that a transaction's log record is complete before it is marked committed. Since NVRAM write latencies are expected to be high, minimizing these ordering constraints is critical for achieving high performance. Recent work has proposed programming interfaces to express NVRAM write ordering constraints to hardware so that NVRAM writes may be coalesced and reordered while preserving necessary constraints. Unfortunately, a straightforward implementation of transactions under these interfaces imposes unnecessary constraints. We show how to remove these dependencies through a variety of techniques, notably, deferring commit until after locks are released. We present a comprehensive analysis contrasting two transaction designs across three NVRAM programming interfaces, demonstrating up to 2.5x speedup. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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