A 20GB/s 256Mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Autor:	Young-Soo Sohn, Gyung-Su Byun, Jung-Hwan Choi, Dong-Jin Lee, Jun-Wan Chai, Soo-In Cho, Jae-Hyoung Lee, Jung Sunwoo, Hoon Lee, Kyu-hyoun Kim, Chan-Kyoung Kim, Chang-Hyun Kim
Rok vydání:	2005
Předmět:	Random access memory Engineering Dynamic random-access memory business.industry Transmitter Electrical engineering Integrated circuit Data rate law.invention Phase-locked loop law Electronic engineering Electrical and Electronic Engineering business Cmos process Dram
Zdroj:	ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
DOI:	10.1109/isscc.2005.1494073
Popis:	A 20-Gb/s 256-Mb DRAM with the proposed PLL and transmitter schemes has been designed and fabricated using an 80-nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with cascaded pre-emphasis transmitter achieves 10-Gb/s/pin data rate.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5d0d96745ea603c63e53c9daa4d9edeb https://doi.org/10.1109/isscc.2005.1494073 Zobrazit plný text záznamu