ATLASpix3 : A high voltage CMOS sensor chip designed for ATLAS Inner Tracker
Autor: | Mathieu Benoit, Annie Meneses, Dms Sultan, P. Pangaud, Raimon Casanova, Alena Larissa Weber, W. Wong, H. Zhang, Rudolf Schimassek, Ivan Peric, E. Vilella, F. Ehrler, Mridula Prathapan |
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Přispěvatelé: | Centre de Physique des Particules de Marseille (CPPM), Aix Marseille Université (AMU)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Aix Marseille Université (AMU) |
Jazyk: | angličtina |
Rok vydání: | 2019 |
Předmět: |
Serial communication
Computer science Physics::Instrumentation and Detectors Integrated circuit 01 natural sciences law.invention Computer Science::Hardware Architecture semiconductor detector: pixel Application-specific integrated circuit law 0103 physical sciences tracking detector [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] Detectors and Experimental Techniques 010306 general physics Engineering & allied operations CMOS sensor 010308 nuclear & particles physics business.industry Detector integrated circuit High voltage ATLAS Chip CMOS electronics: readout interface ddc:620 business Computer hardware electronics: design |
Zdroj: | PoS Topical Workshop on Electronics for Particle Physics Topical Workshop on Electronics for Particle Physics, Sep 2019, Santiago de Compostela, Spain. pp.010, ⟨10.22323/1.370.0010⟩ Scopus-Elsevier Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2019) |
ISSN: | 1824-8039 |
DOI: | 10.22323/1.370.0010⟩ |
Popis: | International audience; ATLASpix3 is a 2×2 cm$^2$ high voltage CMOS sensor chip designed to meet the specifications of outer layers of ATLAS inner tracker. It is compatible with the hybrid pixel sensor ASIC RD53A in terms of electronic interface and geometry. ATLASpix3 is a depleted monolithic CMOS pixel detector which allows the construction of quad modules of the same size as that of hybrid sensors. The readout scheme can be externally configured as triggered or triggerless column drain readout. The hit information is transmitted through a 1.28 Gbit/s serial link. The interface is based on a single command input that is used for providing clock, trigger and configuration commands. Thiscontribution summarizes the detector architecture with focus on the design of its readout circuitry.In addition, simulation results obtained using ReadOut Modelling Environment (ROME), that led to the design of the readout system are discussed. |
Databáze: | OpenAIRE |
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