Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Autor: Sze Pei Lim, Cheng-Ta Ko, Henry Yang, Tony Chen, Cao Xi, Eric Kuah, Zhang Li, Hsing-Hui Wu, Jeffery C. C. Lo, Yu-Hua Chen, Chieh-Lin Chang, Jhih-Yuan Pan, Kim Hwee Tan, John H. Lau, Mian Tao, Junfen Lin, Nelson Fan, Ning Cheng Lee, Iris Xu, Penny Lo, Marc Lin, Margie Li, Ming Li, Ricky Lee, Rozalia Beica, Chia-Hung Lin, Curry Lin
Rok vydání: 2018
Předmět:
Zdroj: International Symposium on Microelectronics. 2018:000057-000063
ISSN: 2380-4505
DOI: 10.4071/2380-4505-2018.1.000057
Popis: The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.
Databáze: OpenAIRE