Evaluation of On-Chip Transmission Line Interconnect Using Wire Length Distribution
| Autor: | Takanori Kyogoku, Kazuya Masu, Junpei Inoue, Shinichiro Gomi, Kenichi Okada, Takumi Uezono, Hiroyuki Ito |
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| Jazyk: | angličtina |
| Rok vydání: | 2005 |
| Předmět: | |
| Zdroj: | ASP-DAC |
| Popis: | On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with wire length distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption. |
| Databáze: | OpenAIRE |
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