Modular PUF coding chain with high-speed Reed-Muller decoder
| Autor: | Andreas Herkle, Holger Mandry, Maurits Ortmanns, Ludwig Kürzinger, Joachim Becker, Robert F. H. Fischer, Sven Müelich |
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| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
050101 languages & linguistics
Speedup Integrierte Schaltung Transistors Electronic Computer science Physical unclonable function Integrated circuits 02 engineering and technology Computer engineering Congresses 0202 electrical engineering electronic engineering information engineering DDC 620 / Engineering & allied operations Generalized concatenated codes 0501 psychology and cognitive sciences DDC 004 / Data processing & computer science Field-programmable gate array PUF Hardware architecture Reed-Muller Field programmable gate arrays business.industry 05 social sciences RM-Code Field programmable gate array Modular design Konkatenationscode 020201 artificial intelligence & image processing Central processing unit ddc:004 ddc:620 business Decoding methods Computer hardware |
| Zdroj: | ISCAS |
| Popis: | Physical Unclonable Functions (PUFs) offer the possibility to produce unique fingerprints for integrated circuits. As raw PUF responses are affected by noise, some post-processing steps are necessary. We present a coding chain test framework for PUFs on Field Programmable Gate Arrays. The framework allows easy exchange, evaluation and comparison of different PUF implementations, coding algorithms and other chain modules. For a testing framework, the execution time of the evaluated algorithm is a bottleneck, since a huge amount of runs are supposed to be done. Hence, we additionally present a new type of Reed-Muller decoder hardware architecture using parallel modules to speed up the decoding process. The decoding time could be decreased by 95% in comparison to existing implementations at the cost of 41 times higher slice count. acceptedVersion |
| Databáze: | OpenAIRE |
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