Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration
| Autor: | Wu Kai, Iris Xu, Ji Hao, Tony Chen, Margie Li, Qing Xiang Yong, Ming Li, Zhang Li, Henry Yang, Zhong Cheng, Sze Pei Lim, Ricky Lee, Koh Sau Wee, Curry Lin, Hsing-Hui Wu, Cheng-Ta Ko, Yiu Ming Cheung, Rozalia Beica, Kim Hwee Tan, Jeffery C. C. Lo, Jiang Ran, Cao Xi, Eric Kuah, John H. Lau, Marc Lin, Yu-Hua Chen, Ning-Cheng Lee, Mian Tao, Nelson Fan, Jhih-Yuan Pan, Chieh-Lin Chang, Eric Ng, Jin Lin |
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| Rok vydání: | 2018 |
| Předmět: |
Materials science
Fabrication Mechanical engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Temperature cycling Photoresist 01 natural sciences Industrial and Manufacturing Engineering law.invention Printed circuit board Reliability (semiconductor) law Plating 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering 010302 applied physics business.industry 020208 electrical & electronic engineering Fan-out 021001 nanoscience & nanotechnology Chip Electronic Optical and Magnetic Materials Capacitor Resist Optoelectronics 0210 nano-technology business |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 8:1561-1572 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2018.2848665 |
| Popis: | The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed. |
| Databáze: | OpenAIRE |
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