Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption
| Autor: | Ernesto Sanchez, Miroslav Valka, Luigi Dilillo, Matteo Sonza Reorda, Mauricio de Carvalho, Paolo Bernardi, Patrick Girard, Alberto Bosio |
|---|---|
| Přispěvatelé: | Politecnico di Torino = Polytechnic of Turin (Polito), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Rok vydání: | 2013 |
| Předmět: |
010302 applied physics
Premature aging Multi-core processor Artificial neural network Computer science AUTOMATIC FUNCTIONAL PROGRAM GENERATION FUNCTIONAL PEAK POWER 02 engineering and technology NEURAL NETWORKS Operand Fault (power engineering) 01 natural sciences Evolutionary computation 020202 computer hardware & architecture Reliability engineering Power (physics) Task (computing) 0103 physical sciences 0202 electrical engineering electronic engineering information engineering EVOLUTIONARY COMPUTING TEST POWER [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Electrical and Electronic Engineering |
| Zdroj: | Journal of Low Power Electronics Journal of Low Power Electronics, American Scientific Publishers, 2013, 9 (2), pp.253-263. ⟨10.1166/jolpe.2013.1259⟩ |
| ISSN: | 1546-1998 |
| Popis: | International audience; High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power consumption during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other side, limiting too much the power consumption during test may reduce the defect coverage. Hence, techniques for identifying upper and lower functional power limits are crucial for delay fault testing. Yet, the task of computing the maximum functional peak power achievable by CPU cores is challenging, since the functional patterns with maximum peak power depend on specific instruction execution order and operands. In this paper, we present a methodology combining neural networks and evolutionary computing for quickly estimating peak power consumption. The method is used within an algorithm for automatic functional program generation used to identify test programs with maximal functional peak power consumption, which are suitable for defining peak power limits under test. The proposed approach was applied on the Intel 8051 CPU core synthesized with a 65 nm industrial technology reducing significant time with respect to old methods. |
| Databáze: | OpenAIRE |
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