Impact of different transistor arrangements on gate variability

Autor: Laurent Artola, Cristina Meinhardt, Guillaume Hubert, Ricardo Reis, Fernanda Lima Kastensmidt, Alexandra L. Zimpeck
Přispěvatelé: Instituto de Informática, Programa de Pós-Graduação em Computação [Porto Alegre] (PPGC), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Universidade Federal de Santa Catarina = Federal University of Santa Catarina [Florianópolis] (UFSC), ONERA / DPHY, Université de Toulouse [Toulouse], PRES Université de Toulouse-ONERA, ONERA-PRES Université de Toulouse
Rok vydání: 2018
Předmět:
DEVICES
Computer science
DIFFERENT TRANSISTOR ARRANGEMENTS
02 engineering and technology
DISPOSITIFS DE TRANSISTORS
01 natural sciences
law.invention
law
Robustness (computer science)
0103 physical sciences
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering
electronic engineering
information engineering
Electrical and Electronic Engineering
Process variability
Safety
Risk
Reliability and Quality
Electronic circuit
010302 applied physics
TECHNOLOGIE FINFET
FINFET TECHNOLOGY
020208 electrical & electronic engineering
Transistor
PROCESS VARIABILITY
Condensed Matter Physics
PROCESSUS DE VARIABILITE
[PHYS.PHYS.PHYS-SPACE-PH]Physics [physics]/Physics [physics]/Space Physics [physics.space-ph]
Atomic and Molecular Physics
and Optics
[SPI.TRON]Engineering Sciences [physics]/Electronics
Surfaces
Coatings and Films
Electronic
Optical and Magnetic Materials
Reliability engineering
Power consumption
Zdroj: Microelectronics Reliability
Microelectronics Reliability, Elsevier, 2018, pp.111-115. ⟨10.1016/j.microrel.2018.06.090⟩
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2018.06.090
Popis: International audience; This paper evaluates a set of complex cells with different transistor arrangements that implement the same logic function. These cells were evaluated under nominal conditions and with gate variability at layout level. The purpose is to verify what topology is more appropriate to increase the robustness of cells regarding the process variability issues. Results emphasize the importance of investigating the effects caused by process variability in FinFET technologies, as the electrical characteristics of circuits suffer significant changes. In general, the best choice is to use the network that the transistor in series is as far as possible to the output node. However, a trade-off needs to be done due to performance and power consumption penalties.
Databáze: OpenAIRE
Externí odkaz: