Information theoretic modeling and analysis for global interconnects with process variations

Autor: Denic, S. Z., Vasic, B., Charalambous, Charalambos D., Chen, J., Wang, J. M.
Přispěvatelé: Charalambous, Charalambos D. [0000-0002-2168-0231]
Rok vydání: 2011
Předmět:
Global interconnect
Engineering
Design
Information theory
Bit-errors
Semiconductor device modeling
Data-communication
Integrated circuit
Upper and lower bounds
Semiconductor technology
law.invention
law
Road-maps
Electronic engineering
Communication application
Electrical and Electronic Engineering
Interconnection
Achievable rate
business.industry
Communication
Semiconductor device manufacture
Communication strategy
Global interconnects
Parasitic parameter
Code rate
Lower bounds
Communication problems
Interconnection networks
Design method
Reliable communication
Nano-meter regimes
Process variation
Harmful effects
CMOS
Code rates
Hardware and Architecture
Bit error rate
Quantum theory
Modeling and analysis
Wafer sizes
Data rates
Bit error rate process variations
business
Quantum chemistry
Software
Interconnect design
Zdroj: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Trans Very Large Scale Integr VLSI Syst
Popis: As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process variations cause errors in data delivering through interconnects. This paper proposes an Information Theory based design method to accommodate process variations. Different from the traditional delay based design metric, the current approach uses achievable rate to relate interconnect designs directly to communication applications. More specifically, the data communication over a typical interconnect, a bus, subject to process variations (uncertain bus), is defined as a communication problem under uncertainty. A data rate, called the achievable rate, is computed for such a bus, which represents the lower bound on the maximal data rate attainable over the bus. When a data rate applied over the bus is smaller than the achievable data rate, a reliable communication can be guaranteed regardless of process variations, i.e., a bit error rate arbitrarily close to zero is achievable. A single communication strategy to combat the process variations is proposed whose code rate is equal to the computed achievable rate. The simulations show that the variations in the interconnect resistivity could have the most harmful effect regarding the achievable rate reduction. Also, the simulations illustrate the importance of taking into account bus parasitic parameters correlations when measuring the influence of the process variations on the achievable rates. © 2006 IEEE. 19 3 397 410
Databáze: OpenAIRE