A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator
| Autor: | Vishnu Unnikrishnan, Waqas Siddiqui, Marko Kosunen, Okko Jarvinen, Teuvo Korhonen, Kimmo Koli, Jussi Ryynanen, Kari Stadius |
|---|---|
| Přispěvatelé: | Jussi Ryynänen Group, Department of Electronics and Nanoengineering, Huawei Technologies, Aalto-yliopisto, Aalto University |
| Rok vydání: | 2021 |
| Předmět: |
bubble error
Physics Bit time General Computer Science data converter Quantization (signal processing) 020208 electrical & electronic engineering Resolution (electron density) General Engineering Phase (waves) real-time cyclic-coupled ring oscillator (CCRO) sub-gate-delay 02 engineering and technology Ring oscillator Converters 020202 computer hardware & architecture time-to-digital converter (TDC) 0202 electrical engineering electronic engineering information engineering Electronic engineering Bandwidth (computing) General Materials Science time resolution Interpolation |
| Zdroj: | IEEE Access. 9:48147-48156 |
| ISSN: | 2169-3536 |
| Popis: | This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, the CCRO phase progression is encoded with a bubble error suppression logic, thereby building resilience to delay mismatches from circuit/layout imperfections. The prototype circuit implemented in a 28 nm CMOS process demonstrates a combination of high resolution and high sample rate over wide range of sample rates. The TDC achieves its peak figure-of-merit (FoM) of 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear resolution and 15.4 ps time resolution, operating from a 0.55 V supply. The TDC demonstrates the highest reported linear resolution of 9.29 bits among converters operating above 100 MS/s, at 125 MS/s and 0.9 V supply, while achieving 4.4 ps time resolution and 0.16 pJ/conv.-step FoM. Further, the real-time quantizing architecture allows fast operation up to 750 MS/s, where the TDC delivers 6-bit linear resolution and 0.48 pJ/conv.-step FoM operating from 0.9 V supply. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|