Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-$\mu$ A Sensing Resolution, and 17.5-nS Read Access Time
| Autor: | Harry H. L. Chuang, Hung-Chang Yu, Lee Chia-Fu, Yi-Chun Shih, Hon-Jarn Lin, Ku-Feng Lin, Jonathan Chang, Yu-Lin Chen, Ta-Ching Yeh, Yu-Der Chih, Po-Hao Lee, Chang Yen-An |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
Magnetoresistive random-access memory business.industry Sense amplifier Circuit design 020208 electrical & electronic engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Chip Compensation (engineering) Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Perpendicular Optoelectronics Wafer Electrical and Electronic Engineering business Access time |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:1029-1038 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2018.2889106 |
| Popis: | A new MRAM reference and sensing circuit that can achieve $\mu \text{A}$ resolution and 17.5 nS read access from −40 °C to 125 °C is presented in this paper. A trimmable current-mode latch-type sense amplifier (CLSA) with hybrid-resistance-reference (HRR) and cell location compensation is proposed to resolve small read margin of MRAM. Silicon data measurement is presented to demonstrate a logic-process compatible, fully functional 16-Mb perpendicular MRAM in 40-nm CMOS process. Similar read circuit design concept can be applied to other technology nodes. Another test chip designed in 22 nm achieves wafer level average raw bit-error-rate (BER) of ~0.2 ppm and less than 2-ppm BER for 95th percentile chip. |
| Databáze: | OpenAIRE |
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