Test yield and quality analysis models of chips
| Autor: | Chung Huang Yeh, Jwu E. Chen |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
0209 industrial biotechnology
Yield (engineering) Computer science Test quality media_common.quotation_subject 020208 electrical & electronic engineering General Engineering Analysis models 02 engineering and technology Test (assessment) Reliability engineering Statistical simulation 020901 industrial engineering & automation Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Quality (business) Test specification media_common |
| Zdroj: | Journal of the Chinese Institute of Engineers. 43:279-287 |
| ISSN: | 2158-7299 0253-3839 |
| DOI: | 10.1080/02533839.2019.1708806 |
| Popis: | In this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor prod... |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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