A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits
| Autor: | Kazuhiro Tsukamoto, S. Imaoka, M. Inuishi, Tsutomu Yoshihara, Yasumasa Tsukamoto, Hirofumi Shinohara, H. Kawashima, Yasuo Yamaguchi, Makoto Yabuuchi, Y. Oda, Koichiro Ishibashi, Mitsuhiko Igarashi, M. Takeuchi, Shigeki Ohbayashi, H. Makino, Koji Nii |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES business.industry Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention Design for manufacturability Nanoelectronics CMOS law Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering System on a chip Static random-access memory Electrical and Electronic Engineering business Electronic circuit |
| Zdroj: | IEEE Journal of Solid-State Circuits. 42:820-829 |
| ISSN: | 0018-9200 |
| Popis: | In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|