Design of an Efficient Low Power Multiplier: Combining Reversible and an Ancient Vedic Method Approach
| Autor: | Shekhar Verma, Mohinder Bassi, Rupendeep Kaur |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Very-large-scale integration
Multidisciplinary 02 engineering and technology Quantum cost Dsp processor 030507 speech-language pathology & audiology 03 medical and health sciences CMOS Power consumption 0202 electrical engineering electronic engineering information engineering Reversible computing 020201 artificial intelligence & image processing Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic 0305 other medical science Mathematics |
| Zdroj: | Indian Journal of Science and Technology. 9 |
| ISSN: | 0974-5645 0974-6846 |
| DOI: | 10.17485/ijst/2016/v9i7/84474 |
| Popis: | Background: Multiplier is very important block which is being used in number of devices like DSP processor and microprocessors. Power consumption by multipliers decides the battery life of all these devices. Researchers are continuously striving for the multiplier which consumes less power but as the most dominant technology till now is CMOS, their efforts are not giving fruitful results due to physical constraints of CMOS device. Methods: In the proposed design used a reversible computing methodology and for circuit designing of multiplier used a QCA Cells. Findings: By combination of reversible computing and ancient Vedic method, a low power and high speed multiplier is proposed. Improvements: With this proposed technique, the Garbage outputs are reduced by 25%, numbers of gates are reduced by 5.40%, numbers of constant inputs are reduced by 6.89%, Quantum cost is reduced by 7.89% and TRLIC factor of this vedic multiplier is reduced by 16.89%. |
| Databáze: | OpenAIRE |
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