Think Fast: A Tensor Streaming Processor (TSP) for Accelerating Deep Learning Workloads
Autor: | Dinesh Maheshwari, Purushotham Kamath, Dennis Abts, Jonathan Ross, Garrin Kimmell, Andrew Bell, Adrian Macias, Jennifer Hwang, Geert Rosseel, Jon Purdy, Richard Czekalski, Jonathan Sparling, Jeff Werner, Michael Beidler, Max Baker, Evan Laforge, Matt Boyd, Rebekah Leslie-Hurd, Brian Kurtz, Jim Sproch, E. R. Creswick, Temesghen Kahsai, Mahitha Venigalla, Gleb Gagarin, Michael Bye, John F. Thompson, Omar Ahmad, Tom Hawkins, Ashay Rane, Mark Wong-VanHaren, Sahil Parmar |
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Rok vydání: | 2020 |
Předmět: |
010302 applied physics
Artificial neural network Dataflow Data parallelism business.industry Computer science Concurrency Deep learning Clock rate 02 engineering and technology Parallel computing 01 natural sciences 020202 computer hardware & architecture Microarchitecture Application-specific integrated circuit 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Artificial intelligence business |
Zdroj: | ISCA |
Popis: | In this paper, we introduce the Tensor Streaming Processor (TSP) architecture, a functionally-sliced microarchitecture with memory units interleaved with vector and matrix deep learning functional units in order to take advantage of dataflow locality of deep learning operations. The TSP is built based on two key observations: (1) machine learning workloads exhibit abundant data parallelism, which can be readily mapped to tensors in hardware, and (2) a simple and deterministic processor with producer-consumer stream programming model enables precise reasoning and control of hardware components, achieving good performance and power efficiency. The TSP is designed to exploit parallelism inherent in machine-learning workloads including instruction-level, memory concurrency, data and model parallelism, while guaranteeing determinism by eliminating all reactive elements in the hardware (e.g. arbiters, and caches). Early ResNet50 image classification results demonstrate 20.4K processed images per second (IPS) with a batch-size of one— a $4 \times$ improvement compared to other modern GPUs and accelerators [44]. Our first ASIC implementation of the TSP architecture yields a computational density of more than 1 TeraOp/s per square mm of silicon for its $25 \times 29$ mm 14nm chip operating at a nominal clock frequency of 900 MHz. The TSP demonstrates a novel hardware-software approach to achieve fast, yet predictable, performance on machine-learning workloads within a desired power envelope. |
Databáze: | OpenAIRE |
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