Design of BiCMOS SRAMs for high‐speed SiGe applications
| Autor: | Ryan Clarke, Mitchell R. LeRoy, John F. McDonald, Russell P. Kraft, Michael Chu, Hadrian Olayvar Aquino, Aamir Zia, Srikumar Raman, Xuelian Liu |
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| Rok vydání: | 2014 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES business.industry Sense amplifier CPU cache Heterojunction bipolar transistor 020208 electrical & electronic engineering Electrical engineering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit design BiCMOS 020202 computer hardware & architecture CMOS Control and Systems Engineering Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Static random-access memory Current-mode logic Electrical and Electronic Engineering business |
| Zdroj: | IET Circuits, Devices & Systems. 8:487-498 |
| ISSN: | 1751-8598 1751-858X |
| DOI: | 10.1049/iet-cds.2013.0375 |
| Popis: | This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs. |
| Databáze: | OpenAIRE |
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