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The semiconductor industry recognizes critical area as the scientific cornerstone metric of a design's fault sensitivity. The ability to accurately and quickly extract critical areas is mandatory when considering design for manufacturability (DFM) motivated changes to a portfolio of chip designs which potentially may translate to random defect yield improvements. IBM has invested in a new technique for computing critical areas based upon Voronoi diagrams. A Voronoi diagram uses the Linfin metric to develop artwork that incorporates nearest neighbor information for every point in a plane; we are able to compute the critical area for electrical shorts, opens, and blockage failure mechanisms. Difficult issues, such as accurately accounting for redundant contacts and vias for a given electrical connection, are also considered. The technique provides a number of advantages over previous techniques, and we compare and contrast the technique with other common industry approaches, such as the Monte Carlo and the shapes expansion techniques. Most noteworthy, the Voronoi-diagram-based approach gives an exact answer, eliminating the integration error found in the other techniques. The technique is also extremely fast; we have seen throughput improvements of more than 60 times compared with our Monte Carlo technique for full chip extraction. The Voronoi-diagram critical area extraction can be extended into a visual form. Previous interactive critical area tools have proven to be difficult to use; because the problem of balancing available spacing - and accounting for common-run and corner interactions - is very difficult, even for an experienced designer. Using Voronoi diagrams, the contribution to critical area can be precisely identified and expressed in the form of error shapes or vectors similar to the output from design rule checkers (DRC). Finally we conclude the paper by briefly discussing some of the other potential applications of Voronoi diagrams relating to DFM |
