Hierarchical Test Compression for SoC Designs
| Autor: | Ming Zhang, Kee Sup Kim |
|---|---|
| Rok vydání: | 2008 |
| Předmět: |
Engineering
business.industry Design for testing Test compression Hardware_PERFORMANCEANDRELIABILITY Reuse Hierarchical test Computer architecture Hardware and Architecture Compression (functional analysis) Embedded system Hardware_INTEGRATEDCIRCUITS System on a chip Electrical and Electronic Engineering business Software |
| Zdroj: | IEEE Design & Test of Computers. 25:142-148 |
| ISSN: | 0740-7475 |
| Popis: | Capitalizing on the larger capacity of today's ICs, designers are using yesterday's chips as modules in today's chips. DFT methodologies, which usually work on a large, flat design, must begin to take this reuse into account. This article shows how to use the X-compact compression technique in a hierarchical environment. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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