ESD robustness improvement for integrated DMOS transistors -the different gate-voltage dependence of It2 between VDMOS and LDMOS transistors
| Autor: | Yasufumi Fujiwara, Shigeto Maegawa, Kenichi Hatasako, T. Kuroi, Akio Uenishi, Fumitoshi Yamamoto |
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| Rok vydání: | 2011 |
| Předmět: |
LDMOS
Engineering Electrostatic discharge business.industry Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Gate voltage law.invention Snapback law Robustness (computer science) Hardware_INTEGRATEDCIRCUITS Optoelectronics LOCOS Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | IEEJ Transactions on Electrical and Electronic Engineering. 6:361-366 |
| ISSN: | 1931-4973 |
| DOI: | 10.1002/tee.20669 |
| Popis: | This paper presents the device-level electrostatic discharge (ESD) robustness improvement for integrated vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate-voltage dependence of the second breakdown current (It2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. |
| Databáze: | OpenAIRE |
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