| Autor: |
Dinesh Maheshwari, Tu Nguyen, Yoshio Nishi, Yuniarto Widjaja, Zvi Or-Bach, Jin-Woo Han, Stefan K. Lai, Christopher Norwood, Pieter Vorenkamp, James Wilson |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
2018 IEEE International Electron Devices Meeting (IEDM). |
| Popis: |
1-transistor and 2-transistor (1T/2T) SRAM are fabricated using 14 nm baseline foundry process without any process modifications. A bi-stable self-latch mechanism is established in a single transistor where its p-type body becomes electrically floating by reverse biased, buried depletion regions from adjacent n-wells. The bit cell operation and the disturb immunity are verified. A unit cell size of $0.039\ \mu \mathrm{m}^{2}$ is achieved, offering >2x area reduction over 6T-SRAM and providing comparable power and performance. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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