Optimized implementation of OpenCL kernels on FPGAs
| Autor: | Kholoud Shata, Adel A. El-Zoghabi, Marwa Elteir |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Speedup 060102 archaeology Computer science business.industry Hardware description language Software development 06 humanities and the arts Parallel computing 01 natural sciences Porting Hardware and Architecture Gate array 0103 physical sciences VHDL Verilog 0601 history and archaeology Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business computer Software Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | Journal of Systems Architecture. 97:491-505 |
| ISSN: | 1383-7621 |
| DOI: | 10.1016/j.sysarc.2019.02.013 |
| Popis: | Recently Field-Programmable Gate Array (FPGA) vendors, such as Altera and Xilinx released an Open Computing Language Software Development Kit (OpenCL SDK). Programming FPGAs using OpenCL can significantly reduce the development time compared to traditional low-level hardware description languages (HDLs), such as Verilog or VHDL. Nevertheless, the direct porting of OpenCL kernels to FPGA without applying the appropriate optimizations can result in significantly under-utilizing the compute capabilities of the device. In this paper, we study some optimization techniques that have not deeply discussed in the previous work despite their importance and impact on the performance of OpenCL kernels designed for FPGA. We have evaluated the impact of applying these optimizations using micro-benchmark and representative workloads. Our results show that the proposed optimizations can significantly improve the performance of OpenCL kernels by up to two order of magnitude i.e., 148.03-fold speedup over the unoptimized kernels. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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