A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance
| Autor: | Jonathan Bachrach, Wen Hau Ma, Franco DeSeta, Elad Alon, Daniel R. Fuhrman, Paul Rigge, Nathan Narevsky, Joseph Cole, Justin Norsworthy, Steven Bailey, Borivoje Nikolic, Matthew Doerflein, Adam Izraelevitz, Steve Shauck, Jim McGrath, Brian Richards, Sergio Montano, Woorham Bae, Chick Markley, Akalu Lentiro, Ronen Shoham, Angie Wang, Mark A. Snowden, Zhongkai Wang, Howard Mao, Munir Razzaque, Richard Lin, Mike Stellfox, Darin Heckendorn, Jaeduk Han, Eric Y. Chang |
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| Rok vydání: | 2019 |
| Předmět: |
Signal processing
Computer science business.industry 020208 electrical & electronic engineering Fast Fourier transform Electrical engineering Mixed-signal integrated circuit Tuner 02 engineering and technology Integrated circuit Chip law.invention CMOS law Filter (video) 0202 electrical engineering electronic engineering information engineering Polyphase system Electrical and Electronic Engineering business |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:2786-2801 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2019.2924090 |
| Popis: | This paper demonstrates a signal analysis system-on-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) followed by a digital tuner, a finite-impulse response (FIR) filter, a polyphase filter, and a fast Fourier transform (FFT) all connected to the five-stage, in-order RISC-V Rocket processor via an AXI4 bus. The generator-based design methodology is detailed, along with the agile design process of producing the fabricated design instance. The $5\,\,\text {mm}\times 5\,\,\text {mm}$ chip is implemented in a 16-nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the application processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art application-specific integrated circuits (ASICs) proves that generators can produce performance-competitive designs. |
| Databáze: | OpenAIRE |
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