| Popis: |
High speed SerDes standards demand higher speed signals for the next generation - 112Gbit/sec. The integrity of signals is affected strongly by the physical characteristics of the printed circuit substrate in a 112Gbit/s high speed device. The effect on circuit performance is primarily shown as insertion loss. Insertion loss mainly consists of conductor loss and dielectric loss. In a build-up laminate substrate using stripline structures for high speed signals, parameters which can be varied to affect the insertion loss are dielectric properties, geometry, and Cu surface finish. Both conductor and dielectric loss benefit from coarse geometry. Coarse geometry for high speed conflicts with microelectronics trends for small size and high density. High speed laminate circuit design will require high wiring layer counts to enable necessary signals. In this development, we designed, fabricated, and evaluated a flip chip laminate assembly using both low loss 33um particle filled and 65um low loss glass cloth reinforced dielectric. The latest generation low loss materials of both types were used. Cu surface roughness in the particle filled layers was 250nm Ra while the glass cloth reinforced (prepreg) layer Cu roughness was 200nm Ra. The configuration was a 65mm square PFCBGA(Plastic Flip Chip Ball Grid Array) laminate cross section consisting of four particle filled dielectric layers, four glass reinforced dielectric layers, two conventional core layers, four glass reinforces dielectric layers, four particle filled dielectric layers. The chip was approximately 25x25mm fully populated with flip chip bump at 150um pitch fabricated in 14 nm technology. Impedance and insertion loss characterization coupons were fabricated in all signal layers. Coupons were placed at controlled angle relative to glass cloth direction to enable evaluation of differential pair skew. In addition to high speed signal characterization, the reliability of high speed signal structures and mixed dielectric via stacks were evaluated. Results indicate a feasible path to 112Gbit/sec HSS SerDes in a manufacturable highly complex (cost) configuration. Currently, the target speed is going to 116Gbit/sec. |
