Wafer edge Shallow Trench Isolation side wall defect reduction on advanced CMOS 0.13µm technology at 0.18µm equipment platform
| Autor: | S Fauziyah, Nurulfajar Abd Manap, Thung Beng Joo, Kader Ibrahim |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Engineering business.industry Semiconductor device fabrication Edge region Electrical engineering 020207 software engineering 02 engineering and technology Technology development 01 natural sciences Optical proximity correction CMOS Shallow trench isolation 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Process optimization Wafer business |
| Zdroj: | 2016 IEEE International Conference on Semiconductor Electronics (ICSE). |
| DOI: | 10.1109/smelec.2016.7573646 |
| Popis: | Nowadays sustaining semiconductor business needs competitiveness improvement which includes scaling down the technology node from CMOS 0.18µm to 0.13µm using similar equipment platforms. In this paper, the enabling new advances technology is through process improvement. The method is complicated and easily caused systematics wafer edge yield loss during initial technology development due to process margin and equipment capability. This paper presents an integrated engineering approach to improve sort yield especially at the wafer edge region. Shallow Trench Isolation (STI) deposition void that causes poly stringer defect is one of the major contributors of yield loss. The process improvement includes understanding caused of defect, process optimization approach that lead to re-design of the STI layout with Optical Proximity Correction (OPC) tagging. The improvement has successfully enable CMOS 0.13µm technology to process at CMOS 0.18µm equipment platform and implemented in production. |
| Databáze: | OpenAIRE |
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