| Autor: |
Bahareh Banijamali, Raghunandan Chaware, Suresh Ramalingam, Myongseob Kim |
| Rok vydání: |
2011 |
| Předmět: |
|
| Zdroj: |
International Symposium on Microelectronics. 2011:000189-000192 |
| ISSN: |
2380-4505 |
| DOI: |
10.4071/isom-2011-tp1-paper1 |
| Popis: |
Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention. High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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