11.39 fJ/conversion‐step 780 kS/s 8 bit switched capacitor‐based area and energy‐efficient successive approximation register ADC in 90 nm complementary metal–oxide–semiconductor
| Autor: | Laxminidhi Tonse, Mujoor Sankaranarayana Bhat, Jagadish Dasarahalli Narasimaiah |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science business.industry 020208 electrical & electronic engineering 8-bit Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit design Switched capacitor 01 natural sciences law.invention Footprint (electronics) Capacitor CMOS Control and Systems Engineering law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Optoelectronics Shaping Electrical and Electronic Engineering business Voltage |
| Zdroj: | IET Circuits, Devices & Systems. 12:249-255 |
| ISSN: | 1751-8598 1751-858X |
| Popis: | In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energy-efficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm 2 and has a figure-of-merit of 11.39 fJ/conv-step. |
| Databáze: | OpenAIRE |
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