A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
| Autor: | Chao-Chieh Li, Sheng-Yao Yang, Sandeep Kumar Goel, Shu-Chun Yang, Tze-Chiang Huang, Kenny Hsieh, Chien-Chun Tsai, King-Ho Tam, Wen-Hung Huang, Ching-Fang Chen, Stefan Rusu, Yu-Chi Chen, Frank Lee, Mei Wong, Chi-Wei Hu, Chin-Ming Fu, Mu-Shan Lin |
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| Rok vydání: | 2020 |
| Předmět: |
Multi-core processor
business.industry Computer science 020208 electrical & electronic engineering Transmitter 02 engineering and technology Supercomputer CMOS Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Bandwidth (computing) Interposer Electrical and Electronic Engineering business Parallel port Computer hardware System bus |
| Zdroj: | IEEE Journal of Solid-State Circuits. 55:956-966 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI. |
| Databáze: | OpenAIRE |
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