A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

Autor: Hae-Kang Jung, Jaehyeok Yang, Ji-Hyo Kang, Yeongmuk Cho, Seon-Yong Cha, Jae-Hoon Cha, Sera Jeong, Minsoo Park, Youngtaek Kim, Hyungsoo Kim, Hongdeuk Kim, Joo-Hyung Chae, Junhyun Chun, Kyung-hoon Kim, Junghwan Ji, Dong-Hyun Kim, Sang-Kwon Lee, Sijun Park, Sangyeon Byeon, Gangsik Lee, Joo-Hwan Cho, Sunho Kim, Ji-Eun Jang, Bo-Ram Kim
Rok vydání: 2022
Předmět:
Zdroj: IEEE Journal of Solid-State Circuits. 57:212-223
ISSN: 1558-173X
0018-9200
DOI: 10.1109/jssc.2021.3114205
Popis: The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3-σ value of the phase skew from 4.16 to 2.25 ps.
Databáze: OpenAIRE
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