HDL FSM Code Generation Using a MIPS-based Assembler
| Autor: | Dominik Meyer, Bernd Klauer, Jan Haase, Marcel Eckert |
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| Rok vydání: | 2019 |
| Předmět: |
Finite-state machine
business.industry Computer science Hardware description language Context (language use) Application-specific integrated circuit Embedded system VHDL Verilog Code generation Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Hardware_LOGICDESIGN computer.programming_language |
| Zdroj: | ISIE |
| DOI: | 10.1109/isie.2019.8781095 |
| Popis: | The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs.This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler. |
| Databáze: | OpenAIRE |
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