Low-cost, wafer level underfilling and reliability testing of flip chip devices
| Autor: | A. Grieve, H.A. Lenos, M.A. Capote, A. Soriano |
|---|---|
| Rok vydání: | 2004 |
| Předmět: |
Materials science
Wafer-scale integration business.industry ComputerApplications_COMPUTERSINOTHERSYSTEMS Hardware_PERFORMANCEANDRELIABILITY Wafer backgrinding Embedded Wafer Level Ball Grid Array Die preparation Hardware_INTEGRATEDCIRCUITS Electronic engineering Optoelectronics Wafer testing Wafer business Probe card Flip chip |
| Zdroj: | 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546). |
| DOI: | 10.1109/ectc.2004.1320312 |
| Popis: | Wafer level underfilling of flip-chip devices offers great potential for high volume packaging at low cost. However, to date, few methods of wafer level underfilling have offered the potential for high assembly yield and high reliability. In this paper, we present a new process technology together with new materials systems for wafer level underfilling of flip-chip devices. This approach utilizes encapsulation of wafers with multiple material layers that are deposited onto an integrated circuit at the wafer level. The enhanced, solder-bumped wafer is then diced into fully encapsulated chips that can be flip-chip attached to printed circuit boards. The advantage of this process is that it requires little additional capital expenditure, yet results in high yield, high reliability assemblies. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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