16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS
| Autor: | Robert M. R. Neff, Bernd Wuppermann, Charles Wu, Dusan Stepanovic, N.J. Guilar, Cheongyuen W. Tsang, John Keane, Ken Nishimura |
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| Rok vydání: | 2017 |
| Předmět: |
Engineering
Comparator Noise measurement business.industry 020208 electrical & electronic engineering Schematic Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Capacitance 020202 computer hardware & architecture law.invention Capacitor CMOS law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) Electronic engineering business |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2017.7870372 |
| Popis: | This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, C bridge . C bridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2V ppd full-scale range when a 1V reference is used. |
| Databáze: | OpenAIRE |
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